{"id":229462,"date":"2026-06-26T17:25:40","date_gmt":"2026-06-26T11:55:40","guid":{"rendered":"https:\/\/www.oliveboard.in\/blog\/?p=229462"},"modified":"2026-06-26T17:30:41","modified_gmt":"2026-06-26T12:00:41","slug":"organisation-of-a-computer","status":"publish","type":"post","link":"https:\/\/www.oliveboard.in\/blog\/organisation-of-a-computer\/","title":{"rendered":"Organisation of a Computer, Free Study Notes PDF &amp; Live Quiz"},"content":{"rendered":"<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_77 counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of content<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 eztoc-toggle-hide-by-default' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/www.oliveboard.in\/blog\/organisation-of-a-computer\/#Organisation_of_a_Computer_for_Bank_Exams_FREE_PDF\" >Organisation of a Computer for Bank Exams, FREE PDF<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/www.oliveboard.in\/blog\/organisation-of-a-computer\/#Organisation_of_a_Computer_for_Bank_Exams_LIVE_Quiz\" >Organisation of a Computer for Bank Exams, LIVE Quiz<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/www.oliveboard.in\/blog\/organisation-of-a-computer\/#Sign_Up\" >Sign Up<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/www.oliveboard.in\/blog\/organisation-of-a-computer\/#Login\" >Login<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/www.oliveboard.in\/blog\/organisation-of-a-computer\/#Forgot_Password\" >Forgot Password<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/www.oliveboard.in\/blog\/organisation-of-a-computer\/#i\" >&nbsp;<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/www.oliveboard.in\/blog\/organisation-of-a-computer\/#Sign_Up-2\" >Sign Up<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/www.oliveboard.in\/blog\/organisation-of-a-computer\/#Login-2\" >Login<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/www.oliveboard.in\/blog\/organisation-of-a-computer\/#Forgot_Password-2\" >Forgot Password<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-10\" href=\"https:\/\/www.oliveboard.in\/blog\/organisation-of-a-computer\/#i-2\" >&nbsp;<\/a><\/li><\/ul><\/nav><\/div>\n\n<p>Organization of a computer is an important topic in the computer awareness section. It focuses on how different hardware components of a computer work together to execute instructions efficiently. Understanding concepts such as the CPU, registers, buses, memory hierarchy, instruction cycle, and input\/output operations helps candidates answer conceptual and application-based questions in the exam. Regular practice of this topic strengthens your understanding of computer architecture and improves accuracy in computer awareness.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-organisation-of-a-computer-for-bank-exams-free-pdf\"><span class=\"ez-toc-section\" id=\"Organisation_of_a_Computer_for_Bank_Exams_FREE_PDF\"><\/span>Organisation of a Computer for Bank Exams, FREE PDF<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>To help you prepare better, we have provided a free organization of computer questions PDF with practice questions and detailed explanations. By practicing from this PDF, you will:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Understand the organization and functions of CPU components<\/li>\n\n\n\n<li>Learn about registers, buses, memory hierarchy, and instruction cycle<\/li>\n\n\n\n<li>Differentiate between concepts such as DMA, polling, interrupts, and addressing modes<\/li>\n\n\n\n<li>Improve conceptual clarity and accuracy for Computer Awareness questions<\/li>\n<\/ul>\n\n\n\n<div class=\"wp-block-buttons is-content-justification-center is-layout-flex wp-container-core-buttons-is-layout-16018d1d wp-block-buttons-is-layout-flex\">\n<div class=\"wp-block-button\"><a class=\"wp-block-button__link wp-element-button\" href=\"https:\/\/www.oliveboard.in\/complete-computer-awareness\/?ref=conttm-computer-awareness\" target=\"_blank\" rel=\"noreferrer noopener\">Download Organisation of a Computer Questions for Bank Exams FREE PDF<\/a><\/div>\n<\/div>\n\n\n\n<h2 class=\"wp-block-heading\" id=\"h-organisation-of-a-computer-for-bank-exams-live-quiz\"><span class=\"ez-toc-section\" id=\"Organisation_of_a_Computer_for_Bank_Exams_LIVE_Quiz\"><\/span>Organisation of a Computer for Bank Exams, LIVE Quiz<span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Organization of a computer questions your understanding of how a computer processes instructions and how its internal components communicate with each other. Our live quizzes help you master important concepts such as the fetch-decode-execute cycle, CPU registers, control unit, ALU, memory management, system buses, and computer architecture.<\/p>\n\n\n\n<!DOCTYPE html>\n<html lang=\"en\">\n<head>\n<meta charset=\"UTF-8\">\n<link rel=\"stylesheet\" href=\"https:\/\/courses.oliveboard.in\/edge\/css\/login-modal-for-blog.css\">\n\n<style>\n#quiz-1-sticky-header {\n  position: sticky;\n  top: 0;\n  z-index: 100;\n  background: #1565c0;\n  color: #fff;\n  padding: 12px 20px;\n  border-radius: 10px 10px 0 0;\n  display: flex;\n  justify-content: space-between;\n  align-items: center;\n  font-size: 16px;\n  font-weight: bold;\n  box-shadow: 0 2px 8px rgba(0,0,0,0.2);\n  margin: -20px -20px 20px -20px;\n}\n\n#quiz-1-score-badge {\n  background: rgba(255,255,255,0.2);\n  padding: 4px 12px;\n  border-radius: 20px;\n  font-size: 15px;\n  white-space: nowrap;\n}\n#quiz-1 * { box-sizing: border-box; }\n\n#quiz-1 .quiz-container {\n  max-width: 700px;\n  margin: auto;\n  padding: 20px;\n  background: #fff;\n  border-radius: 14px;\n  box-shadow: 0 6px 16px rgba(0,0,0,0.12);\n}\n\n#quiz-1 h2 {\n  text-align: center;\n}\n\n#quiz-1 .question {\n  margin-bottom: 22px;\n}\n\n#quiz-1 .question p {\n  font-weight: bold;\n}\n\n#quiz-1 button {\n  width: 100%;\n  padding: 12px;\n  margin: 6px 0;\n  border: none;\n  border-radius: 6px;\n  background: #e0e0e0;\n  color: #000;\n  font-size: 16px;\n  cursor: pointer;\n}\n\n#quiz-1 button:hover {\n  background: #d5d5d5;\n}\n\n#quiz-1 button.correct {\n  background: #4caf50;\n  color: #000;\n}\n\n#quiz-1 button.wrong {\n  background: #f44336;\n  color: #000;\n}\n\n#quiz-1 button.locked {\n  pointer-events: none;\n}\n\n\/* SUMMARY *\/\n#quiz-1 .final-summary {\n  margin-top: 40px;\n  padding: 20px;\n  border-radius: 14px;\n  background: #fafafa;\n  border: 2px solid #4caf50;\n}\n\n#quiz-1 .final-summary h3 {\n  text-align: center;\n  margin-bottom: 20px;\n}\n\n#quiz-1 .summary-row {\n  display: grid;\n  grid-template-columns: 120px 1fr 40px;\n  gap: 10px;\n  align-items: center;\n  margin-bottom: 12px;\n  font-weight: bold;\n}\n\n#quiz-1 .summary-bar {\n  height: 14px;\n  background: #ddd;\n  border-radius: 10px;\n  overflow: hidden;\n}\n\n#quiz-1 .bar-fill {\n  height: 100%;\n  width: 0%;\n}\n\n#quiz-1 .bar-attempted { background: #2196f3; }\n#quiz-1 .bar-correct { background: #4caf50; }\n#quiz-1 .bar-wrong { background: #f44336; }\n#quiz-1 .bar-unattempted { background: #9e9e9e; width: 100%; }\n\n#quiz-1 .final-score {\n  text-align: center;\n  font-size: 22px;\n  margin-top: 20px;\n}\n\n#quiz-1 .score-value {\n  font-size: 30px;\n  margin-left: 8px;\n}\n<\/style>\n<\/head>\n\n<body>\n<div id=\"quiz-1\">\n  <div class=\"quiz-container\">\n<div id=\"quiz-1-sticky-header\">\n  <span> Organisation of a Computer (Part 1) <\/span>\n  <span id=\"quiz-1-score-badge\">Score: <strong id=\"quiz-1-score-value\">0.00<\/strong><\/span>\n<\/div>\n\n    <!-- QUESTIONS -->\n\n   <div class=\"question\" data-answered=\"false\">\n    <p>1. Which of the following is NOT one of the five basic functional units of a computer?<\/p>\n    <button data-correct=\"false\">Arithmetic Logic Unit<\/button>\n    <button data-correct=\"false\">Control Unit<\/button>\n    <button data-correct=\"true\">Compiler Unit<\/button>\n    <button data-correct=\"false\">Input Unit<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>2. In a Von Neumann architecture, instructions and data are stored in:<\/p>\n    <button data-correct=\"false\">Separate instruction and data memories<\/button>\n    <button data-correct=\"true\">The same unified memory<\/button>\n    <button data-correct=\"false\">Registers only<\/button>\n    <button data-correct=\"false\">Cache only<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>3. The &#8216;Von Neumann bottleneck&#8217; refers to:<\/p>\n    <button data-correct=\"false\">Limited register count<\/button>\n    <button data-correct=\"false\">Slow ALU operations<\/button>\n    <button data-correct=\"true\">The single bus between CPU and memory limiting throughput<\/button>\n    <button data-correct=\"false\">Inability to support floating point<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>4. Harvard Architecture is commonly used in:<\/p>\n    <button data-correct=\"false\">Desktop personal computers<\/button>\n    <button data-correct=\"false\">Mainframe systems<\/button>\n    <button data-correct=\"true\">Digital Signal Processors (DSPs) and microcontrollers<\/button>\n    <button data-correct=\"false\">Cloud servers<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>5. Which register always holds the address of the NEXT instruction to be fetched?<\/p>\n    <button data-correct=\"false\">Instruction Register (IR)<\/button>\n    <button data-correct=\"true\">Program Counter (PC)<\/button>\n    <button data-correct=\"false\">Memory Address Register (MAR)<\/button>\n    <button data-correct=\"false\">Accumulator (ACC)<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>6. The Memory Buffer Register (MBR) is used to:<\/p>\n    <button data-correct=\"false\">Hold the opcode of the current instruction<\/button>\n    <button data-correct=\"true\">Temporarily hold data being transferred to\/from memory<\/button>\n    <button data-correct=\"false\">Store the address of a memory operand<\/button>\n    <button data-correct=\"false\">Count the number of memory accesses<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>7. What is the function of the Accumulator register?<\/p>\n    <button data-correct=\"false\">Store the base address for indexed addressing<\/button>\n    <button data-correct=\"false\">Store the return address for subroutine calls<\/button>\n    <button data-correct=\"true\">Store the intermediate and final results of ALU operations<\/button>\n    <button data-correct=\"false\">Hold the current value of the stack pointer<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>8. Which flag in the Status Register is set when the result of an ALU operation is zero?<\/p>\n    <button data-correct=\"false\">Sign flag<\/button>\n    <button data-correct=\"false\">Carry flag<\/button>\n    <button data-correct=\"false\">Overflow flag<\/button>\n    <button data-correct=\"true\">Zero flag<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>9. In the fetch-decode-execute cycle, what happens immediately after the instruction is fetched?<\/p>\n    <button data-correct=\"false\">The instruction is executed<\/button>\n    <button data-correct=\"true\">The instruction is decoded<\/button>\n    <button data-correct=\"false\">The result is written back to memory<\/button>\n    <button data-correct=\"false\">The PC is decremented<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>10. During the Fetch stage of the instruction cycle, which two registers are primarily involved?<\/p>\n    <button data-correct=\"false\">ACC and IR<\/button>\n    <button data-correct=\"true\">PC and MAR<\/button>\n    <button data-correct=\"false\">SP and MBR<\/button>\n    <button data-correct=\"false\">GPR and PSW<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>11. In which addressing mode is the operand directly specified as part of the instruction itself?<\/p>\n    <button data-correct=\"false\">Direct Mode<\/button>\n    <button data-correct=\"false\">Indirect Mode<\/button>\n    <button data-correct=\"true\">Immediate Mode<\/button>\n    <button data-correct=\"false\">Register Mode<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>12. Which addressing mode provides the FASTEST operand access?<\/p>\n    <button data-correct=\"false\">Indirect Mode<\/button>\n    <button data-correct=\"false\">Direct Mode<\/button>\n    <button data-correct=\"false\">Immediate Mode<\/button>\n    <button data-correct=\"true\">Register Mode<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>13. In indirect addressing mode, the instruction contains:<\/p>\n    <button data-correct=\"false\">The operand value directly<\/button>\n    <button data-correct=\"false\">The address of the operand<\/button>\n    <button data-correct=\"true\">The address of the address of the operand<\/button>\n    <button data-correct=\"false\">An offset to be added to the PC<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>14. Indexed addressing mode is most commonly used for:<\/p>\n    <button data-correct=\"false\">Calling subroutines<\/button>\n    <button data-correct=\"true\">Accessing elements of an array<\/button>\n    <button data-correct=\"false\">Fetching the next sequential instruction<\/button>\n    <button data-correct=\"false\">Handling interrupt vectors<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>15. Relative addressing mode computes the effective address as:<\/p>\n    <button data-correct=\"true\">PC + Displacement<\/button>\n    <button data-correct=\"false\">Base Register + Displacement<\/button>\n    <button data-correct=\"false\">Index Register + Constant<\/button>\n    <button data-correct=\"false\">Stack Pointer + Offset<\/button>\n<\/div>\n\n    <!-- FINAL SUMMARY -->\n    <div class=\"final-summary\">\n      <h3>Quiz Summary <\/h3>\n\n      <div class=\"summary-row\">\n        <span>Attempted<\/span>\n        <div class=\"summary-bar\"><div class=\"bar-fill bar-attempted\" data-summary=\"attempted\"><\/div><\/div>\n        <span data-count=\"attempted\">0<\/span>\n      <\/div>\n\n      <div class=\"summary-row\">\n        <span>Correct<\/span>\n        <div class=\"summary-bar\"><div class=\"bar-fill bar-correct\" data-summary=\"correct\"><\/div><\/div>\n        <span data-count=\"correct\">0<\/span>\n      <\/div>\n\n      <div class=\"summary-row\">\n        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}\n\n#quiz-2 .quiz-container {\n  max-width: 700px;\n  margin: auto;\n  padding: 20px;\n  background: #fff;\n  border-radius: 14px;\n  box-shadow: 0 6px 16px rgba(0,0,0,0.12);\n}\n\n#quiz-2 h2 {\n  text-align: center;\n}\n\n#quiz-2 .question {\n  margin-bottom: 22px;\n}\n\n#quiz-2 .question p {\n  font-weight: bold;\n}\n\n#quiz-2 button {\n  width: 100%;\n  padding: 12px;\n  margin: 6px 0;\n  border: none;\n  border-radius: 6px;\n  background: #e0e0e0;\n  color: #000;\n  font-size: 16px;\n  cursor: pointer;\n}\n\n#quiz-2 button:hover {\n  background: #d5d5d5;\n}\n\n#quiz-2 button.correct {\n  background: #4caf50;\n  color: #000;\n}\n\n#quiz-2 button.wrong {\n  background: #f44336;\n  color: #000;\n}\n\n#quiz-2 button.locked {\n  pointer-events: none;\n}\n\n\/* SUMMARY *\/\n#quiz-2 .final-summary {\n  margin-top: 40px;\n  padding: 20px;\n  border-radius: 14px;\n  background: #fafafa;\n  border: 2px solid #4caf50;\n}\n\n#quiz-2 .final-summary h3 {\n  text-align: center;\n  margin-bottom: 20px;\n}\n\n#quiz-2 .summary-row {\n  display: grid;\n  grid-template-columns: 120px 1fr 40px;\n  gap: 10px;\n  align-items: center;\n  margin-bottom: 12px;\n  font-weight: bold;\n}\n\n#quiz-2 .summary-bar {\n  height: 14px;\n  background: #ddd;\n  border-radius: 10px;\n  overflow: hidden;\n}\n\n#quiz-2 .bar-fill {\n  height: 100%;\n  width: 0%;\n}\n\n#quiz-2 .bar-attempted { background: #2196f3; }\n#quiz-2 .bar-correct { background: #4caf50; }\n#quiz-2 .bar-wrong { background: #f44336; }\n#quiz-2 .bar-unattempted { background: #9e9e9e; width: 100%; }\n\n#quiz-2 .final-score {\n  text-align: center;\n  font-size: 22px;\n  margin-top: 20px;\n}\n\n#quiz-2 .score-value {\n  font-size: 30px;\n  margin-left: 8px;\n}\n<\/style>\n<\/head>\n\n<body>\n<div id=\"quiz-2\">\n  <div class=\"quiz-container\">\n<div id=\"quiz-2-sticky-header\">\n  <span> Organisation of a Computer (Part 2) <\/span>\n  <span id=\"quiz-2-score-badge\">Score: <strong id=\"quiz-2-score-value\">0.00<\/strong><\/span>\n<\/div>\n\n    <!-- QUESTIONS -->\n\n    <div class=\"question\" data-answered=\"false\">\n    <p>16. RISC architecture is characterized by:<\/p>\n    <button data-correct=\"false\">Complex variable-length instructions, many memory addressing modes<\/button>\n    <button data-correct=\"true\">Simple fixed-length instructions, load-store design, large register file<\/button>\n    <button data-correct=\"false\">Microprogrammed control unit, few registers<\/button>\n    <button data-correct=\"false\">Memory-to-memory operations, variable execution cycles<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>17. Which of the following is an example of a CISC architecture?<\/p>\n    <button data-correct=\"false\">ARM Cortex-A series<\/button>\n    <button data-correct=\"false\">MIPS R3000<\/button>\n    <button data-correct=\"true\">Intel x86<\/button>\n    <button data-correct=\"false\">SPARC V9<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>18. VLIW (Very Long Instruction Word) architecture is designed to:<\/p>\n    <button data-correct=\"false\">Execute one operation per clock cycle by keeping instructions short<\/button>\n    <button data-correct=\"true\">Issue multiple operations in a single long instruction word simultaneously<\/button>\n    <button data-correct=\"false\">Reduce instruction cache misses through short instructions<\/button>\n    <button data-correct=\"false\">Avoid the need for registers altogether<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>19. A key advantage of RISC over CISC for pipelining is:<\/p>\n    <button data-correct=\"false\">RISC instructions are more feature-rich<\/button>\n    <button data-correct=\"true\">RISC has fixed-length simple instructions, making pipeline stages uniform and easier to implement<\/button>\n    <button data-correct=\"false\">RISC eliminates all data hazards<\/button>\n    <button data-correct=\"false\">RISC supports more memory addressing modes<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>20. In a load-store ISA (typical of RISC), memory access is:<\/p>\n    <button data-correct=\"false\">Allowed in all arithmetic and logical instructions<\/button>\n    <button data-correct=\"true\">Restricted to dedicated LOAD and STORE instructions only<\/button>\n    <button data-correct=\"false\">Not supported; all data stays in registers permanently<\/button>\n    <button data-correct=\"false\">Combined with ALU operations in the same instruction<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>21. What is the primary goal of pipelining in a CPU?<\/p>\n    <button data-correct=\"false\">To reduce the number of registers needed<\/button>\n    <button data-correct=\"false\">To decrease power consumption<\/button>\n    <button data-correct=\"true\">To increase instruction throughput by overlapping stages of multiple instructions<\/button>\n    <button data-correct=\"false\">To eliminate the need for a cache<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>22. In a 5-stage pipeline (IF, ID, EX, MEM, WB), what is the ideal throughput for instructions?<\/p>\n    <button data-correct=\"false\">One instruction every 5 cycles<\/button>\n    <button data-correct=\"true\">One instruction every cycle (after the pipeline is filled)<\/button>\n    <button data-correct=\"false\">Five instructions every cycle<\/button>\n    <button data-correct=\"false\">One instruction every 3 cycles<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>23. Average Memory Access Time (AMAT) for a cache with hit time h, miss rate m, and miss penalty p is:<\/p>\n    <button data-correct=\"true\">h + m \u00d7 p<\/button>\n    <button data-correct=\"false\">h \u00d7 m + p<\/button>\n    <button data-correct=\"false\">(h + p) \/ m<\/button>\n    <button data-correct=\"false\">h \/ (1 &#8211; m) + p<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>24. Virtual memory allows a program to use an address space that is:<\/p>\n    <button data-correct=\"false\">Exactly equal to the physical RAM installed<\/button>\n    <button data-correct=\"true\">Potentially larger than the physical RAM available<\/button>\n    <button data-correct=\"false\">Limited to the size of the CPU registers<\/button>\n    <button data-correct=\"false\">Fixed at 4 KB regardless of hardware<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>25. A TLB (Translation Lookaside Buffer) is used to speed up:<\/p>\n    <button data-correct=\"false\">Disk I\/O operations<\/button>\n    <button data-correct=\"true\">Virtual-to-physical address translation<\/button>\n    <button data-correct=\"false\">Cache line replacement decisions<\/button>\n    <button data-correct=\"false\">Floating-point arithmetic<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>26. A &#8216;page fault&#8217; occurs when:<\/p>\n    <button data-correct=\"false\">The CPU accesses a register that doesn&#8217;t exist<\/button>\n    <button data-correct=\"true\">A required page is not currently in physical RAM and must be fetched from disk<\/button>\n    <button data-correct=\"false\">The page table entry is marked as present<\/button>\n    <button data-correct=\"false\">The TLB is full and cannot store more entries<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>27. &#8216;Thrashing&#8217; in virtual memory systems refers to:<\/p>\n    <button data-correct=\"false\">Excessive TLB misses causing slow address translation<\/button>\n    <button data-correct=\"true\">Rapid, excessive page faults causing the CPU to spend most time swapping pages rather than executing<\/button>\n    <button data-correct=\"false\">Cache lines being frequently replaced due to conflict misses<\/button>\n    <button data-correct=\"false\">A program using more registers than available<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>28. Belady&#8217;s Anomaly is observed in which page replacement algorithm?<\/p>\n    <button data-correct=\"false\">LRU<\/button>\n    <button data-correct=\"false\">Optimal (OPT)<\/button>\n    <button data-correct=\"true\">FIFO<\/button>\n    <button data-correct=\"false\">Clock \/ Second-Chance<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>29. The Optimal (OPT \/ Belady&#8217;s Optimal) page replacement algorithm replaces the page:<\/p>\n    <button data-correct=\"false\">That was used least recently<\/button>\n    <button data-correct=\"false\">That was brought in first<\/button>\n    <button data-correct=\"true\">That will not be used for the longest time in the future<\/button>\n    <button data-correct=\"false\">That has the lowest reference count<\/button>\n<\/div>\n\n<div class=\"question\" data-answered=\"false\">\n    <p>30. DMA (Direct Memory Access) is primarily used to:<\/p>\n    <button data-correct=\"false\">Allow the CPU to bypass cache during I\/O<\/button>\n    <button data-correct=\"true\">Transfer large blocks of data between I\/O devices and memory without continuous CPU involvement<\/button>\n    <button data-correct=\"false\">Enable multiple CPUs to share a single memory bus<\/button>\n    <button data-correct=\"false\">Accelerate floating-point calculations in the ALU<\/button>\n<\/div>\n\n    <!-- FINAL SUMMARY -->\n    <div class=\"final-summary\">\n      <h3>Quiz Summary <\/h3>\n\n      <div class=\"summary-row\">\n        <span>Attempted<\/span>\n        <div class=\"summary-bar\"><div class=\"bar-fill bar-attempted\" data-summary=\"attempted\"><\/div><\/div>\n        <span data-count=\"attempted\">0<\/span>\n      <\/div>\n\n      <div class=\"summary-row\">\n        <span>Correct<\/span>\n        <div class=\"summary-bar\"><div class=\"bar-fill bar-correct\" data-summary=\"correct\"><\/div><\/div>\n        <span data-count=\"correct\">0<\/span>\n      <\/div>\n\n      <div class=\"summary-row\">\n        <span>Wrong<\/span>\n        <div class=\"summary-bar\"><div class=\"bar-fill bar-wrong\" data-summary=\"wrong\"><\/div><\/div>\n        <span data-count=\"wrong\">0<\/span>\n      <\/div>\n\n      <div class=\"summary-row\">\n        <span>Unattempted<\/span>\n        <div class=\"summary-bar\"><div class=\"bar-fill bar-unattempted\" data-summary=\"unattempted\"><\/div><\/div>\n        <span data-count=\"unattempted\">0<\/span>\n      <\/div>\n\n      <div class=\"final-score\">\n        Final Score: <span class=\"score-value\" data-score>0.0<\/span>\n      <\/div>\n    <\/div>\n\n  <\/div>\n<\/div>\n<div class=\"modal modal-obls\" id=\"modal-signup\">\n        <div class=\"modal-background\"><\/div>\n        <div class=\"modal-content\">\n           <div class=\"obls-group\" id=\"obls-group1\">\n               <div class=\"obls-blk\">\n  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Check Eligibility with FREE Live Tool<\/a><\/li>\n<li><a class=\"wp-block-latest-posts__post-title\" href=\"https:\/\/www.oliveboard.in\/blog\/sbi-po-prelims-pyps\/\">SBI PO Question Papers, Shift-Wise PYPs, Download PDFs<\/a><\/li>\n<li><a class=\"wp-block-latest-posts__post-title\" href=\"https:\/\/www.oliveboard.in\/blog\/prepare-like-sbi-po-air-1-niranjan-jains-winning-strategy\/\">Prepare Like SBI PO AIR 1: Niranjan Jain&#8217;s Winning Strategy<\/a><\/li>\n<li><a class=\"wp-block-latest-posts__post-title\" href=\"https:\/\/www.oliveboard.in\/blog\/sbi-po-job-profile-and-responsibilities\/\">SBI PO Job Profile, Roles &amp; Career Growth Details<\/a><\/li>\n<li><a class=\"wp-block-latest-posts__post-title\" href=\"https:\/\/www.oliveboard.in\/blog\/sbi-po-work-life-balance\/\">Is the SBI PO Job Hectic? Check job profile and work-life balance<\/a><\/li>\n<\/ul>\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n","protected":false},"excerpt":{"rendered":"<p>Organization of a computer is an important topic in the computer awareness section. It focuses on how different hardware components<\/p>\n","protected":false},"author":60,"featured_media":246392,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1,31],"tags":[18579,111],"class_list":["post-229462","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-articles","category-bank-exams","tag-organisation-of-a-computer","tag-sbi-po","generate-columns","tablet-grid-50","mobile-grid-100","grid-parent","grid-50"],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v26.6 (Yoast SEO v26.6) - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Organisation of a Computer PDF, Free Study Notes &amp; Live Quiz<\/title>\n<meta name=\"description\" content=\"Download the Organization of a Computer PDF. Learn CPU, registers, buses, memory hierarchy, and the instruction cycle and practice with live quizzes.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.oliveboard.in\/blog\/organisation-of-a-computer\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Organisation of a Computer, Free Study Notes PDF &amp; Live Quiz\" \/>\n<meta property=\"og:description\" content=\"Organization of a computer is an important topic in the computer awareness section. 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