Organization of a computer is an important topic in the computer awareness section. It focuses on how different hardware components of a computer work together to execute instructions efficiently. Understanding concepts such as the CPU, registers, buses, memory hierarchy, instruction cycle, and input/output operations helps candidates answer conceptual and application-based questions in the exam. Regular practice of this topic strengthens your understanding of computer architecture and improves accuracy in computer awareness.
Organisation of a Computer for Bank Exams, FREE PDF
To help you prepare better, we have provided a free organization of computer questions PDF with practice questions and detailed explanations. By practicing from this PDF, you will:
- Understand the organization and functions of CPU components
- Learn about registers, buses, memory hierarchy, and instruction cycle
- Differentiate between concepts such as DMA, polling, interrupts, and addressing modes
- Improve conceptual clarity and accuracy for Computer Awareness questions
Organisation of a Computer for Bank Exams, LIVE Quiz
Organization of a computer questions your understanding of how a computer processes instructions and how its internal components communicate with each other. Our live quizzes help you master important concepts such as the fetch-decode-execute cycle, CPU registers, control unit, ALU, memory management, system buses, and computer architecture.
1. Which of the following is NOT one of the five basic functional units of a computer?
2. In a Von Neumann architecture, instructions and data are stored in:
3. The ‘Von Neumann bottleneck’ refers to:
4. Harvard Architecture is commonly used in:
5. Which register always holds the address of the NEXT instruction to be fetched?
6. The Memory Buffer Register (MBR) is used to:
7. What is the function of the Accumulator register?
8. Which flag in the Status Register is set when the result of an ALU operation is zero?
9. In the fetch-decode-execute cycle, what happens immediately after the instruction is fetched?
10. During the Fetch stage of the instruction cycle, which two registers are primarily involved?
11. In which addressing mode is the operand directly specified as part of the instruction itself?
12. Which addressing mode provides the FASTEST operand access?
13. In indirect addressing mode, the instruction contains:
14. Indexed addressing mode is most commonly used for:
15. Relative addressing mode computes the effective address as:
Quiz Summary
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16. RISC architecture is characterized by:
17. Which of the following is an example of a CISC architecture?
18. VLIW (Very Long Instruction Word) architecture is designed to:
19. A key advantage of RISC over CISC for pipelining is:
20. In a load-store ISA (typical of RISC), memory access is:
21. What is the primary goal of pipelining in a CPU?
22. In a 5-stage pipeline (IF, ID, EX, MEM, WB), what is the ideal throughput for instructions?
23. Average Memory Access Time (AMAT) for a cache with hit time h, miss rate m, and miss penalty p is:
24. Virtual memory allows a program to use an address space that is:
25. A TLB (Translation Lookaside Buffer) is used to speed up:
26. A ‘page fault’ occurs when:
27. ‘Thrashing’ in virtual memory systems refers to:
28. Belady’s Anomaly is observed in which page replacement algorithm?
29. The Optimal (OPT / Belady’s Optimal) page replacement algorithm replaces the page:
30. DMA (Direct Memory Access) is primarily used to:
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